View AD6645ASQ-80_1561506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

14-bit, 80 msps/105 msps a/d converter ad6645 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2002C2008 analog devices, inc. all rights reserved. features snr = 75 db, f in 15 mhz, up to 105 msps snr = 72 db, f in 200 mhz, up to 105 msps sfdr = 89 dbc, f in 70 mhz, up to 105 msps 100 dbfs multitone sfdr if sampling to 200 mhz sampling jitter: 0.1 ps 1.5 w power dissipation differential analog inputs pin compatible to ad6644 twos complement digital output format 3.3 v cmos compatible data-ready for output latching applications multichannel, multimode receivers base station infrastructures amps, is-136, cdma, gsm, w-cdma single channel digital receivers antenna array processing communications instrumentation radars, infrared imaging instrumentation general description the ad6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (adc ). all necessary functions, including track-and-hold (t/h) and reference, are included on the chip to provide a complete conversion solution. the ad6645 provides cmos-compatible digital outputs. it is the fourth generation in a wideband adc family, preceded by the ad9042 (12-bit, 41 msps), the ad6640 (12-bit, 65 msps, if sampling), and the ad6644 (14-bit, 40 msps/65 msps). designed for multichannel, multimode receivers, the ad6645 is part of the analog devices, inc., softcell? transceiver chipset. the ad6645 maintains 100 db multitone, spurious-free dynamic range (sfdr) through the second nyquist band. this breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the adc. noise performance is exceptional; typical signal-to-noise ratio (snr) is 74.5 db through the first nyquist band. the ad6645 is built on the analog devices extra fast complementary bipolar (xfcb) process and uses an innovative, multipass circuit architecture. units are available in thermally enhanced 52-lead powerquad 4 (lqfp_pq4) and 52-lead exposed pad (tqfp_ep) packages specified from ?40c to +85c at 80 msps and ?10c to +85c at 105 msps. product highlights 1. if sampling. the ad6645 maintains outstanding ac performance up to input frequencies of 200 mhz, suitable for multicarrier 3g wideband cellular if sampling receivers. 2. pin compatibility. the adc has the same footprint and pin layout as the ad6644 14-bit, 40 msps/65 msps adc. 3. sfdr performance and oversampling. multitone sfdr performance of 100 dbfs can reduce the requirements of high end rf components and allows the use of receive signal processors, such as the ad6620, ad6624 / ad6624a , or ad6636 . functional block diagram 5 6 5 ad6645 ain ain vref encode encode gnd dmid ovr dry d13 msb d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb adc3 th5 th4 dac2 adc2 th3 a2 dac1 digital error correction logic th2 adc1 th1 a1 2.4v internal timing dv cc av cc 02647-001 figure 1.
ad6645 rev. d | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dc specifications ......................................................................... 3 ? digital specifications ................................................................... 4 ? ac specifications .......................................................................... 4 ? switching specifications .............................................................. 5 ? absolute maximum ratings ............................................................ 7 ? thermal resistance ...................................................................... 7 ? explanation of test levels ............................................................7 ? esd caution...................................................................................7 ? pin configuration and function descriptions ..............................8 ? typical performance characteristics ..............................................9 ? equivalent circuits ......................................................................... 14 ? terminology .................................................................................... 15 ? theory of operation ...................................................................... 17 ? applying the ad6645 ................................................................ 17 ? layout information ........................................................................ 19 ? jitter considerations .................................................................. 19 ? outline dimensions ....................................................................... 24 ? ordering guide .......................................................................... 24 ? revision history 10/08rev. c to rev. d added tqfp_ep package ............................................ throughout renamed thermal characteristics section thermal resistance section ................................................................................................ 7 added table 6; renumbered sequentially .................................... 7 moved equivalent circuits section .............................................. 14 moved terminology section ......................................................... 15 changes to table 9 .......................................................................... 20 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 12/06rev. b to rev. c updated format .................................................................. universal changes to specifications ................................................................ 3 changes to jitter considerations section .................................... 19 changes to table 8, bill of materials ............................................ 20 changes to figure 43, evaluation board schematic .................. 21 changes to figure 44 and figure 46 ............................................. 22 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 7/03rev. a to rev. b. changes to title ................................................................................ 1 changes to features .......................................................................... 1 changes to product description ..................................................... 1 changes to specifications ................................................................. 3 changes to absolute maximum ratings ........................................ 7 changes to ordering guide .......................................................... 24 updated outline dimensions ....................................................... 20 6/02rev. 0 to rev. a. change to dc specifications ........................................................... 3
ad6645 rev. d | page 3 of 24 specifications dc specifications av cc = 5 v, dv cc = 3.3 v; t min and t max at rated speed grade, unless otherwise noted. table 1. AD6645ASQ-80/ad6645asv-80 ad6645asq-105/ad6645asv-105 parameter temp test level min typ max min typ max unit resolution 14 14 bits accuracy no missing codes full ii guaranteed guaranteed offset error full ii ?10 +1.2 +10 ?10 +1.2 +10 mv gain error full ii ?10 0 +10 ?10 0 +10 % fs differential nonlinearity (dnl) full ii ?1.0 0.25 +1.5 ?1.0 0.5 +1.5 lsb integral nonlinearity (inl) full v 0.5 1.5 lsb temperature drift offset error full v 1.5 1.5 ppm/c gain error full v 48 48 ppm/c power supply rejection ratio (psrr) 25c v 1.0 1.0 mv/v reference out (vref) 1 full v 2.4 2.4 v analog inputs (ain, ain ) differential input voltage range full v 2.2 2.2 v p-p differential input resistance full v 1 1 k differential input capacitance 25c 1.5 1.5 pf power supply supply voltages av cc full ii 4.75 5.0 5.25 4.75 5.0 5.25 v dv cc full ii 3.0 3.3 3.6 3.0 3.3 3.6 v supply current iav cc (av cc = 5.0 v) full ii 275 320 275 320 ma idv cc (dv cc = 3.3 v) full ii 32 45 32 45 ma rise time 2 av cc full iv 250 5.0 250 ms power consumption full ii 1.5 1.75 1.5 1.75 w 1 vref is provided for setting the common-mode offset of a differential amplifier, such as the ad8138, when a dc-coupled analog input is required. vref should be buffered if used to drive additional circuit functions. 2 specified for dc supplies with linear rise time characteristics.
ad6645 rev. d | page 4 of 24 digital specifications av cc = 5 v, dv cc = 3.3 v; t min and t max at rated speed grade, unless otherwise noted. table 2. test AD6645ASQ-80/ad6645asv-80 ad6645asq-105/ad6645asv-105 parameter temp level min typ max min typ max unit encode inputs (encode, encode ) differential input voltage 1 full iv 0.4 0.4 v p-p differential input resistance 25c v 10 10 k differential input capacitance 25c v 2.5 2.5 pf logic outputs (d13 to d0, dry, ovr) logic compatibility cmos cmos logic 1 voltage (dv cc = 3.3 v) 2 full ii 2.85 dv cc ? 2 2.85 dv cc ? 2 v logic 0 voltage (dv cc = 3.3 v) 2 full ii 0.2 0.5 0.2 0.5 v output coding twos complement twos complement dmid full v dv cc /2 dv cc /2 v 1 all ac specifications tested by driving encode and encode differentially. 2 digital output logic levels: dv cc = 3.3 v, c load = 10 pf. capacitive loads >10 pf degrades performance. ac specifications all ac specifications tested by driving encode and encode differentially. av cc = 5 v, dv cc = 3.3 v; encode, encode , t min and t max at rated speed grade, unless otherwise noted. table 3. test AD6645ASQ-80/ ad6645asv-80 ad6645asq-105/ ad6645asv-105 parameter temp level min typ max min typ max unit conditions snr analog input @ ?1 dbfs 25c v 75.0 75.0 db at 15.5 mhz full ii 72.5 74.5 db at 30.5 mhz 25c i 72.5 74.5 db at 37.7 mhz full ii 72.0 73.5 72.0 73.5 db at 70.0 mhz 25c v 73.0 73.0 db at 150.0 mhz 25c v 72.0 72.0 db at 200.0 mhz sinad analog input @ ?1 dbfs 25c v 75.0 75.0 db at 15.5 mhz full ii 72.5 74.5 db at 30.5 mhz 25c i 72.5 74.5 db at 37.7 mhz full v 73.0 73.0 db at 70.0 mhz 25c v 68.5 67.5 db at 150.0 mhz 25c v 62.5 62.5 db at 200.0 mhz worst harmonic (second or third) analog input @ ?1 dbfs 25c v 93.0 93.1 dbc at 15.5 mhz full ii 85.0 93.0 dbc at 30.5 mhz 25c i 85.0 93.0 dbc at 37.7 mhz full v 89.0 87.0 dbc at 70.0 mhz 25c v 70.0 70.0 dbc at 150.0 mhz 25c v 63.5 63.5 dbc at 200.0 mhz
ad6645 rev. d | page 5 of 24 test AD6645ASQ-80/ ad6645asv-80 ad6645asq-105/ ad6645asv-105 parameter temp level min typ max min typ max unit conditions worst harmonic (fourth or higher) analog input @ ?1 dbfs 25c v 96.0 96.0 dbc at 15.5 mhz full ii 85.0 95.0 dbc at 30.5 mhz 25c i 86.0 95.0 dbc at 37.7 mhz full v 90.0 90.0 dbc at 70.0 mhz 25c v 90.0 90.0 dbc at 150.0 mhz 25c v 88.0 88.0 dbc at 200.0 mhz two-tone sfdr 25c v 100 98.0 dbfs at 30.5 mhz 1 , 2 25c v 100 98.0 dbfs at 55.0 mhz 1 , 3 25c v 98.0 dbfs at 70.0 mhz 1 , 4 two-tone imd rejection 2 , 3 f1, f2 @ ?7 dbfs 25c v 90 90 dbc analog input bandwidth 25c v 270 270 mhz 1 analog input signal power swep t from ?10 dbfs to ?100 dbfs. 2 f1 = 30.5 mhz, f2 = 31.5 mhz. 3 f1 = 55.25 mhz, f2 = 56.25 mhz. 4 f1 = 69.1 mhz, f2 = 71.1 mhz. switching specifications av cc = 5 v, dv cc = 3.3 v; encode, encode , t min and t max at rated speed grade, unless otherwise noted. table 4. test AD6645ASQ-80/ ad6645asv-80 ad6645asq-105/ ad6645asv-105 parameter symbol temp level min typ max min typ max unit encode input parameters 1 maximum conversion rate full ii 80 105 msps minimum conversion rate full iv 30 30 msps encode pulse width high, t ench 2 full iv 5.625 4.286 ns full v 6.25 4.75 ns encode pulse width low, t encl 2 full iv 5.625 4.286 ns full v 6.25 4.75 ns encode period 1 t enc full v 12.5 9.5 ns encode/data-ready encode rising to data-ready falling t dr full v 1.0 2.0 3.1 1.0 2.0 3.1 ns encode rising to data-ready rising t e_dr full v t ench + t dr t ench + t dr ns 50% duty cycle full v 7.3 8.3 9.4 5.7 6.75 7.9 ns encode/data (d13:0), ovr encode to data falling low t e_fl full v 2.4 4.7 7.0 2.4 4.7 7.0 ns encode to data rising low 3 t e_rl full v 1.4 3.0 4.7 1.4 3.0 4.7 ns encode to data delay 3 (hold time) t h_e full v 1.4 3.0 4.7 1.4 3.0 4.7 ns encode to data delay (setup time) t s_e full v t enc ? t e_fl(max) t enc ? t e_fl(max) ns t enc ? t e_fl(typ) t enc ? t e_fl(typ) ns t enc ? t e_fl(min) t enc ? t e_fl(min) ns 50% duty cycle full v 5.3 7.6 10.0 2.3 4.8 7.0 ns
ad6645 rev. d | page 6 of 24 test AD6645ASQ-80/ ad6645asv-80 ad6645asq-105/ ad6645asv-105 parameter symbol temp level min typ max min typ max unit data-ready (dry 4 )/data(d13:0),, ovr data-ready to data delay (hold time) t h_dr full v note 5 5 note 5 5 50% duty cycle full v 6.6 7.2 7.9 5.1 5.7 6.4 ns data-ready to data delay (setup time) t s_dr full v note 5 5 note 5 5 50% duty cycle full v 2.1 3.6 5.1 0.6 2.1 3.5 ns aperture delay t a 25c v ?500 ?500 ps aperture uncertainty (jitter) t j 25c v 0.1 0.1 ps rms 1 several timing parameters are a function of t enc and t ench . 2 several timing parameters are a function of t encl and t ench . 3 encode to data delay (hold time) is the absolute minimum propagation delay through the adc, t e_rl = t h_e . 4 dry is an inverted and delayed version of the encode clock. any change in the duty cycle of the clock will correspondingly cha nge the duty cycle of dry. 5 data-ready to data delay (t h_dr and t s_dr ) is calculated relative to rated speed grade and is dependent on t enc and duty cycle. t s_dr t a ain n n + 1 n + 2 n + 3 n + 4 t enc t ench t encl t e_fl t e_rl t e_dr t s_e t h_e t dr t h_dr n n ? 1 n ? 3 d[13:0], ovr dry n + 4 n + 3 n + 2 n + 1 n encode, encode n ? 2 2647-002 0 figure 2. timing diagram
ad6645 rev. d | page 7 of 24 absolute maximum ratings table 5. parameter rating electrical av cc voltage 0 v to 7 v dv cc voltage 0 v to 7 v analog input voltage 0 v to av cc analog input current 25 ma digital input voltage 0 v to av cc digital output current 4 ma environmental operating temperature range (ambient) ad6645-80 ?40c to +85c ad6645-105 ?10c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the heat sink of the ad6645asvz, 52-lead tqfp_ep (sv-52-1) package must be soldered to the pcb gnd plane to meet thermal specifications. table 6. thermal characteristics package type rating 52-lead tqfp_ep ja (0 m/sec airflow) 1, 2, 3 23c/w, soldered heat sink jma (1.0 m/sec airflow) 2, 3, 4, 5 17c/w, soldered heat sink jc 6, 7 2c/w, soldered heat sink 52-lead lqfp_pq4 ja (0 m/sec airflow) 1, 2, 3 30c/w, unsoldered heat sink jma (1.0 m/sec airflow) 2, 3, 4, 5 24c/w, unsoldered heat sink ja (0 m/sec airflow) 1, 2, 3 23c/w, soldered heat sink jma (1.0 m/sec airflow) 2, 3, 4, 5 17c/w, soldered heat sink jc 6, 7 2c/w 1 per jedec jesd51-2 (heat sink soldered to pcb). 2 2s2p jedec test board. 3 values of ja are provided for package comparison and pcb design considerations. 4 per jedec jesd51-6 (heat sink soldered to pcb). 5 airflow increases heat dissipation, effectively reducing ja . furthermore, the more metal that is directly in contact with the package leads from metal traces, throughholes, ground, and power planes, the more ja is reduced. 6 per mil-std-883, method 1012.1. 7 values of jc are provided for package comparison and pcb design considerations when an extern al heat sink is required. va lu e s of ja are provided for package comparison and pcb design considerations. ja can be used for a first-order approximation of t j by the equation t j = t a + ( ja pd ) where: t a is the ambient temperature (c). pd is the power dissipation (w). explanation of test levels i. 100% production tested. ii. 100% production tested at 25c and guaranteed by design and characterization at temperature extremes. iii. sample tested only. iv. parameter is guaranteed by design and characterization testing. v. parameter is a typical value only. esd caution
ad6645 rev. d | page 8 of 24 pin configuration and fu nction descriptions notes 1. dnc = do not connect. 2. exposed pad. connect the exposed pad to gnd. pin 1 identifier ad6645 top view (not to scale) 1 dv cc 2 gnd 3 vref 4 gnd 5 encode 6 encode 7 gnd 8 av cc 9 av cc 10 gnd 11 14 ain 12 ain 13 gnd av cc 15 gnd 16 av cc 17 gnd 18 av cc 19 gnd 20 c1 21 gnd 22 av cc 23 gnd 24 c2 25 gnd 26 av cc 27 gnd 28 av cc 29 gnd 30 av cc 31 dnc 32 ovr 33 dv cc 34 gnd 35 dmid 36 d0 (lsb) 37 40 d1 38 d2 39 d3 d4 41 d5 42 gnd 43 dv cc 44 d6 45 d7 46 d8 47 d9 48 d10 49 d11 50 d12 51 d13 (msb) 52 dry 02647-003 figure 3. pin configuration table 7. pin function descriptions pin number mnemonic description 1, 33, 43 dv cc 3.3 v power supply (digital) output stage only. 2, 4, 7, 10, 13, 15, 17, 19, 21, 23, 25, 27, 29, 34, 42 gnd ground. 3 vref 2.4 v reference. bypass to ground with a 0.1 f microwave chip capacitor. 5 encode encode input. conversion initiated on rising edge. 6 encode complement of encode , differential input. 8, 9, 14, 16, 18, 22, 26, 28, 30 av cc 5 v analog power supply. 11 ain analog input. 12 ain complement of ain, differential analog input. 20 c1 internal voltage reference. bypass to ground with a 0.1 f chip capacitor. 24 c2 internal voltage reference. bypass to ground with a 0.1 f chip capacitor. 31 dnc do not connect this pin. 32 ovr overrange bit. a logic level high indicates analog input exceeds fs. 35 dmid output data voltage midpoint. approximately equal to (dv cc )/2. 36 d0 (lsb) digital output bit (least significant bit); twos complement. 37 to 41, 44 to 50 d1 to d5, d6 to d12 digital output bits in twos complement. 51 d13 (msb) digital output bit (most significant bit); twos complement. 52 dry data-ready output. 53 (epad) exposed paddle (epad) exposed pad. connect the exposed pad to gnd.
ad6645 rev. d | page 9 of 24 typical performance characteristics frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 5 0 10152025303540 encode = 80msps ain = 2.2mhz @ ?1dbfs snr = 75.0db sfdr = 93.0dbc 02647-010 figure 4. single tone @ 2.2 mhz frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 5 0 10152025303540 encode = 80msps ain = 15.5mhz @ ?1dbfs snr = 75.0db sfdr = 93.0dbc 0 2647-011 figure 5. single tone @ 15.5 mhz frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 5 0 10152025303540 encode = 80msps ain = 29.5mhz @ ?1dbfs snr = 74.5db sfdr = 93.0dbc 02647-012 figure 6. single tone @ 29.5 mhz frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 encode = 80msps ain = 69.1mhz @ ?1dbfs snr = 73.5db sfdr = 89.0dbc 5 0 10152025303540 02647-013 figure 7. single tone @ 69.1 mhz frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 encode = 80msps ain = 150mhz @ ?1dbfs snr = 73.0db sfdr = 70.0dbc 5 0 10152025303540 02647-014 figure 8. single tone @ 150 mhz frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 encode = 80msps ain = 200mhz @ ?1dbfs snr = 72.0db sfdr = 64.0dbc 5 0 10152025303540 02647-015 figure 9. single tone @ 200 mhz
ad6645 rev. d | page 10 of 24 frequency (mhz) snr (db) 72.0 72.5 73.0 73.5 74.0 74.5 75.0 75.5 0 10203040506070 t = ?40c t = +85c t = +25c encode = 80msps @ ain = ?1dbfs temp = ?40c, +25c, +85c 02647-016 figure 10. signal-to-noise ratio (snr) vs. frequency analog input frequency (mhz) worst-case harmonic (dbc) 80 82 84 86 88 90 92 94 t = +25c t = ?40c, +85c encode = 80msps @ ain = ?1dbfs temp = ?40c, +25c, +85c 0 10203040506070 0 2647-017 figure 11. worst-case harmonics vs. analog input frequency analog frequency (mhz) snr (db) 70 71 72 73 74 75 76 0 20 40 60 80 100 120 140 160 180 200 encode = 80msps @ ain = ?1dbfs temp = 25c 02647-018 figure 12. signal-to-noise ratio (snr) vs. analog frequency (if) analog frequency (mhz) harmonics (dbc) 60 65 70 80 90 100 75 85 95 worst other spur harmonics (second, third) encode = 80msps @ ain = ?1dbfs temp = 25c 0 20 40 60 80 100 120 140 160 180 200 02647-019 figure 13. harmonics vs. analog frequency (if) analog input power level (dbfs) worst-case spurious (dbfs and dbc) 0 10 20 30 40 50 60 70 80 90 100 110 dbc 120 dbfs encode = 80msps ain = 30.5mhz sfdr = 90db reference line ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 02647-020 figure 14. single-tone sfdr @ 30.5 mhz analog input power level (dbfs) worst case spurious (dbfs and dbc) 0 10 20 30 40 50 60 70 80 90 100 110 dbc 120 dbfs ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr = 90db reference line encode = 80msps ain = 69.1mhz 0 2647-021 figure 15. single-tone sfdr @ 69.1 mhz
ad6645 rev. d | page 11 of 24 frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2f1 ? f2 2f2 + f1 2f1 + f2 f2 ? f1 2f2 ? f1 f1 + f2 encode = 80msps ain = 30.5mhz, 31.5mhz (?7dbfs) no dither 5 0 10152025303540 02647-022 figure 16. two-tone sfdr @ 30.5 mhz and 31.5 mhz input power level (f1 = f2 dbfs) worst-case spurious (dbfs and dbc) 0 10 20 30 40 50 60 70 80 90 100 110 dbc dbfs sfdr = 90db reference line encode = 80msps f1 = 30.5mhz f2 = 31.5mhz ?77 ?67 ?57 ?47 ?37 ?27 ?17 ?7 02647-023 figure 17. two-tone sfdr @ 30.5 mhz and 31.5 mhz encode frequency (mhz) 65 70 80 90 worst spur @ ain = 2.2mhz snr @ ain = 2.2mhz 75 85 95 100 snr, worst-case spurious (db and dbc) 15 30 45 60 75 90 105 02647-024 figure 18. snr, worst-case spurious vs. encode @ 2.2 mhz 2f2 ? f1 frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) f1 + f2 2f1 ? f2 2f2 + f1 2f1 + f2 f2 ? f1 encode = 80msps ain = 55.25mhz, 56.25mhz (?7dbfs) no dither 5 0 10152025303540 02647-025 figure 19. two-tone sfdr @ 55.25 mhz and 56.25 mhz input power level (f1 = f2 dbfs) worst-case spurious (dbfs and dbc) 0 10 20 30 40 50 60 70 80 90 100 110 dbc dbfs sfdr = 90db reference line encode = 80msps f1 = 55.25mhz f2 = 56.25mhz ?77 ?67 ?57 ?47 ?37 ?27 ?17 ?7 0 2647-026 figure 20. two-tone sfdr @ 55.25 mhz and 56.25 mhz encode frequency (mhz) 65 70 80 90 worst spur @ ain = 69.1mhz snr @ ain = 69.1mhz 75 85 95 snr, worst-case spurious (db and dbc) 15 30 45 60 75 90 105 02647-027 figure 21. snr, worst-case spurious vs. encode @ 69.1 mhz
ad6645 rev. d | page 12 of 24 frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5 3 2 6 4 amplitude (dbfs) encode = 80.0msps ain = 30.5mhz @ ?29.5dbfs no dither 5 0 10152025303540 02647-028 figure 22. 1 m sample fft without dither analog input level (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 worst-case spurious (dbc) 90 80 70 60 50 40 30 20 10 0 sfdr = 90db reference line encode = 80.0msps ain = 30.5mhz no dither 02647-029 figure 23. sfdr without dither frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 encode = 76.8msps ain = 69.1mhz @ ?1dbfs snr = 73.5db sfdr = 89.0dbc 5 0 10152025303540 02647-030 figure 24. single tone @ 69.1 mhz, encode = 76.8 msps frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5 3 2 6 4 amplitude (dbfs) 5 0 10152025303540 encode = 80.0msps ain = 30.5mhz @ ?29.5dbfs with dither @ ?19.2 dbm 02647-031 figure 25. 1 m sample fft with dither analog input level (dbfs) 0 10 20 30 40 50 60 70 80 90 100 110 worst-case spurious (dbc) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 sfdr = 90db reference line sfdr = 100db reference line encode = 80.0msps ain = 30.5mhz with dither @ ?19.2dbm 02647-032 figure 26. sfdr with dither frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 2 6 5 4 3 encode = 76.8msps ain = w-cdma @ 69.1mhz 0 5 10 15 20 25 30 35 40 02647-033 figure 27. w-cdma tone @ 69.1 mhz, encode = 76.8 msps
ad6645 rev. d | page 13 of 24 frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) 5 0 10152025303540 encode = 76.8msps ain = 2w-cdma @ 59.6mhz 02647-034 6 54 2 3 frequency (mhz) amplitude (dbfs) encode = 76.8msps ain = w-cdma @ 140mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 5 0 10152025303540 0 2647-036 figure 28. two w-cdma carriers @ 59.6 mhz, encode = 76.8 msps figure 30. w-cdma tone @ 140 mhz, encode = 76.8 msps 23 645 amplitude (dbfs) frequency (mhz) encode = 61.44msps ain = w-cdma @ 190mhz ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 02647-037 frequency (mhz) ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 amplitude (dbfs) encode = 61.44msps ain = 4w-cdma @ 46.08mhz 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 02647-035 figure 31. w-cdma tone @ 190 mhz, encode = 61.44 msps figure 29. four w-cdma carriers @ 46.08 mhz, encode = 61.44 msps
ad6645 rev. d | page 14 of 24 equivalent circuits buf t/h buf buf t/h 500 ? ain ain 500 ? vref av cc v ch v cl v ch av cc v cl 02647-004 figure 32. analog input stage loads loads 10k ? 10k ? 10k ? 10k ? encode encode av cc av cc av cc av cc 02647-005 figure 33. encode inputs c1, c2 av cc av cc av cc v ref current mirror 0 2647-006 figure 34. compensation pin, c1 or c2 dv cc current mirror d0 to d13, ovr, dry dv cc v ref current mirror 02647-007 figure 35. digital output stage 2.4v av cc av cc vref 100a 02647-008 figure 36. 2.4 v reference 10k ? dmid 10k ? dv cc 02647-009 figure 37. dmid reference
ad6645 rev. d | page 15 of 24 terminology analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay the delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. the peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180 out of phase. the peak-to-peak differential is computed by rotating the inputs phase 180and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code width from an ideal 1 lsb step. encode pulse width/duty cycle pulse width high is the minimum amount of time that the encode pulse should be left in a high state to achieve rated performance; pulse width low is the minimum time that the encode pulse should be left in a low state. see timing implications of changing t ench in table 4 . at a given clock rate, these specifications define an acceptable encode duty cycle. full-scale input power the full-scale input power is expressed in dbm and can be calculated by using the following equation: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = ? 001.0 2 log10 input z rmsscalefull v scalefull power harmonic distortion, second the ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dbc. harmonic distortion, third the ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dbc. integral nonlinearity the deviation of the transfer function from a reference line measured in fractions of 1 lsb using a best straight line determined by a least square curve fit. maximum conversion rate the encode rate at which parametric testing is performed. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. noise (for any range within the adc) ? ? ? ? ? ? ?? = 10 10001.0 dbfs dbc dbm noise signal snr fs z v where: z is the input impedance. fs is the full scale of the device for the frequency in question. snr is the value for the particular input level. signal is the signal level within the adc reported in db below full scale. this value includes both thermal noise and quantiza- tion noise. output propagation delay the delay between a differential crossing of encode and encode and the time when all output data bits are within valid logic levels. power supply rejection ratio (pssr) the ratio of a change in input offset voltage to a change in power supply voltage. power supply rise time the time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the adc. the dc level is measured at the supply pin(s) of the adc. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
ad6645 rev. d | page 16 of 24 spurious-free dynamic range (sfdr) the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. may be reported in dbc (that is, degrades as signal level is lowered) or dbfs (always related back to converter full scale). two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dbc. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component may or may not be an imd product, and may be reported in dbc (that is, degrades as signal level is lowered) or in dbfs (always related back to converter full scale). worst other spur the ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics), reported in dbc.
ad6645 rev. d | page 17 of 24 theory of operation the ad6645 adc employs a three-stage subrange architecture. this design approach achieves the required accuracy and speed while maintaining low power and small die size. as shown in the functional block diagram (see figure 1 ), the ad6645 has complementary analog input pins, ain and ain . each analog input is centered at 2.4 v and should swing 0.55 v around this reference (see ). because ain and figure 32 ain are 180 out of phase, the differential analog input signal is 2.2 v p-p. both analog inputs are buffered prior to the first track-and-hold, th1. the high state of the encode pulse places th1 in hold mode. the held value of th1 is applied to the input of a 5-bit coarse adc1. the digital output of adc1 drives a 5-bit digital- to-analog converter, dac1. dac1 requires 14 bits of precision that is achieved through laser trimming. the output of dac1 is subtracted from the delayed analog signal at the input of th3 to generate a first residue signal. th2 provides an analog pipeline delay to compensate for the digital delay of adc1. the first residual signal is applied to a second conversion stage consisting of a 5-bit adc2, a 5-bit dac2, and a pipeline th4. the second dac requires 10 bits of precision, which is met by the process with no trim. the input to th5 is a second residual signal generated by subtracting the quantized output of dac2 from the first residual signal held by th4. th5 drives a final 6-bit adc3. the digital outputs from adc1, adc2, and adc3 are added together and corrected in the digital error correction logic to generate the final output data. the result is a 14-bit parallel digital cmos-compatible word, coded as twos complement. applying the ad6645 encoding the ad6645 the ad6645 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. maintaining 14-bit accuracy places a premium on encode clock phase noise. snr performance can easily degrade by 3 db to 4 db with 70 mhz analog input signals when using a high jitter clock source. see the an-501 application note, aperture uncertainty and adc system performance , for complete details. for optimum performance, the ad6645 must be clocked differentially. the encode signal is usually ac-coupled into the encode and encode pins via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 38 shows one preferred method for clocking the ad6645. the clock source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit excessive amplitude swings from the clock into the ad6645 to approximately 0.8 v p-p differential. this helps to prevent the large voltage swings of the clock from feeding through to other portions of the ad6645 and limits the noise presented to the encode inputs. encode encode t1-4t ad6645 hsms2812 diodes 0.1f clock source 02647-038 figure 38. crystal clock oscillator, differential encode if a low jitter clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins, as shown in figure 39 . the mc100el16 (or same family) from on semiconductor offers excellent jitter performance. encode encode ad6645 v t vt ecl/ pecl 0.1f 0.1f 02647-039 figure 39. differential ecl for encode driving the analog inputs as with most new high speed, high dynamic range adcs, the analog input to the ad6645 is differential. differential inputs improve on-chip performance as signals are processed through attenuation and gain stages. most of the improvement is a result of differential analog stages having high rejection of even-order harmonics. there are also benefits at the pcb level. first, differential inputs have high common-mode rejection of stray signals, such as ground and power noise. second, they provide good rejection of common-mode signals, such as local oscillator feedthrough. the ad6645 analog input voltage range is offset from ground by 2.4 v. each analog input connects through a 500 resistor to the 2.4 v bias voltage and to the input of a differential buffer (see figure 32 ). the resistor network on the input properly biases the followers for maximum linearity and range. therefore, the analog source driving the ad6645 should be ac-coupled to the input pins. because the differential input impedance of the ad6645 is 1 k, the analog input power requirement is only ?2 dbm, simplifying the driver amplifier in many cases. to take full advantage of this high input impedance, a 20:1 rf transformer is required. this is a large ratio and can result in unsatisfactory performance. in this case, a lower step-up ratio can be used. the recommended method for driving the differential analog input of the ad6645 is to use a 4:1 rf transformer. for example, if r t is set to 60.4 and r s is set to 25 , along with a 4:1 impedance ratio transformer, the input would match to a 50 source with a full-scale drive of 4.8 dbm. series resistors (r s ) on the secondary side of the transformer should be used to isolate the transformer from the a/d.
ad6645 rev. d | page 18 of 24 this limits the amount of dynamic current from the a/d flowing back into the secondary of the transformer. the 50 impedance matching can also be incorporated on the secondary side of the transformer, as shown in the evaluation board schematic (see figure 43 ). ain ain adt4-1wt ad6645 a n a log input signal r s r s 0.1f r t 02647-040 figure 40. transformer-coupled analog input circuit in applications where dc coupling is required, a differential output op amp, such as the ad8138 , can be used to drive the ad6645 (see figure 41 ). the ad8138 op amp provides single- ended-to-differential conversion, which reduces overall system cost and minimizes layout requirements. ad6645 ain ain ad8138 5v 499 ? 499 ? 499 ? 499 ? vref digital outputs 25 ? 25 ? v ocm c f c f v in 02647-041 figure 41. dc-coupled analog input circuit power supplies care should be taken when selecting a power source. the use of linear dc supplies with rise times of <45 ms is highly recommended. switching supplies tend to have radiated components that can be received by the ad6645. decouple each of the power supply pins as close to the package as possible using 0.1 f chip capacitors. the ad6645 has separate digital and analog power supply pins. the analog supplies are av cc and the digital supply pins are dv cc . although analog and digital supplies can be tied together, the best performance is achieved when the supplies are separate because the fast digital output swings can couple switching currents back into the analog supplies. note that av cc must be held within 5% of 5 v. the ad6645 is specified for dv cc = 3.3 v, a common supply for digital asics. digital outputs care must be taken when designing the data receivers for the ad6645. it is recommended that the digital outputs drive a series resistor followed by a gate, such as the 74lcx574. to minimize capacitive loading, there should be only one gate on each output pin. an example of this is shown in the evaluation board schematic of figure 43 . the digital outputs of the ad6645 have a constant output slew rate of 1 v/ns. a typical cmos gate combined with a pcb trace have a load of approximately 10 pf. therefore, as each bit switches, 10 ma (10 pf 1 v 1 ns) of dynamic current per bit flow in or out of the device. a full-scale transition can cause up to 140 ma (14 bits 10 ma/bit) of current to flow through the output stages. place the series resistors as close to the ad6645 as possible to limit the amount of current that can flow into the output stage. these switching currents are confined between ground and dv cc . standard ttl gates should be avoided because they can add appreciably to the dynamic switching currents of the ad6645. note that extra capacitive loading increases output timing and invalidates timing specifications. digital output timing is guaranteed for output loads up to 10 pf. digital output states for given analog input levels are shown in table 8 . grounding for optimum performance, it is highly recommended that a common ground be used between the analog and digital power planes. the primary concern with splitting grounds is that dynamic currents may be forced to travel significant distances in the system before recombining back at the common source ground. this can result in a large, undesirable ground loop. the most common place for this to occur is on the digital outputs of the adc. ground loops can contribute to digital noise being coupled back onto the adc front end. this can manifest itself as either harmonic spurs, or very high-order spurious products that can cause excessive spikes on the noise floor. this noise coupling is less likely to occur at lower clock speeds because the digital noise has more time to settle between samples. in general, splitting the analog and digital grounds can frequently contribute to undesirable emi-rfi and should, therefore, be avoided. conversely, if not properly implemented, common grounding can actually impose additional noise issues because the digital ground currents ride on top of the analog ground currents in close proximity to the adc input. to further minimize the potential for noise coupling, it is highly recommended that multiple ground return traces/vias be placed such that the digital output currents do not flow back toward the analog front end but are routed quickly away from the adc. this does not require a split in the ground plane and can be accomplished by simply placing substantial ground connections directly back to the supply at a point between the analog front end and the digital outputs. in addition, the judicious use of ceramic chip capacitors between the power supply and ground planes helps to suppress digital noise. the layout should incorporate enough bulk capacitance to supply the peak current requirements during switching periods.
ad6645 rev. d | page 19 of 24 layout information the schematic of the evaluation board (see figure 43 ) represents a typical implementation of the ad6645. a multi- layer board is recommended to achieve best results. it is highly recommended that high quality, ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. the pinout of the ad6645 facilitates ease of use in the implementation of high frequency, high resolution design practices. all of the digital outputs are segregated to two sides of the chip, with the inputs on the opposite side for isolation purposes. care should be taken when routing the digital output traces. to prevent coupling through the digital outputs into the analog portion of the ad6645, minimal capacitive loading should be placed on these outputs. it is recommended that a fanout of only one gate should be used for all ad6645 digital outputs. the layout of the encode circuit is equally critical. any noise received on this circuitry results in corruption in the digitization process and lower overall performance. the encode clock must be isolated from the digital outputs and the analog inputs. table 8. twos complement output coding ain level ain level output state output code vref + 0.55 v vref ? 0.55 v positive fs 01 1111 1111 1111 vref vref midscale 00 0/11 1 vref ? 0.55 v vref + 0.55 v negative fs 10 0000 0000 0000 jitter considerations the snr for an adc can be predicted. when normalized to adc codes, the following equation accurately predicts the snr based on three terms: jitter, average dnl error, and thermal noise. each of these terms contributes to the noise within the converter. () 2/1 2 2 2 2 22 2 1 2log20 76.1 ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? + + ? = n rmsnoise n rms j analog v tf snr where: f analog is the analog input frequency. t j rms is the rms jitter of the encode (rms sum of encode source and internal encode circuitry). is the average dnl of the adc (typically 0.41 lsb). n is the number of bits in the adc. v noise rms is the voltage rms thermal noise that refers to the analog input of the adc (typically 0.9 lsb rms). for a 14-bit adc, such as the ad6645, aperture jitter can greatly affect the snr performance as the analog frequency is increased. figure 42 shows a family of curves that demonstrate the expected snr performance of the ad6645 as jitter increases. the chart is derived from the preceding equation. for a complete discussion of aperture jitter, see the an-756 application note, sampled systems and the effects of clock phase noise and jitter . the an-756 application note can be found on www.analog.com . jitter (ps) 55 snr (dbfs) 60 65 70 75 80 ain = 110mhz ain = 150mhz ain = 190mhz ain = 30mhz ain = 70mhz 0 0.1 0.2 0.3 0.4 0.5 0.6 02647-042 figure 42. snr vs. jitter
ad6645 rev. d | page 20 of 24 table 9. ad6645/pcb bill of materials quantity 80 msps quantity 105 msps reference id description manufacturer supplier part no. 1 1 pcb printed circuit board, ad6645 engineering evaluation board pcsm 6645ee01d rev d 4 4 c1, c2, c31, c38 capacitor, tantalum, smt bcaptajc, 10 f, 16 v, 10% kemet t491c106k016as 8 8 c3, c7 to c10, c16, c30 1 , c32 capacitor, ceramic, smt 0508, 0.1 f, 16 v, 10% presidio components 0508x7r104k16vp3 9 9 c4, c15, c22 to c26, c29, (c33) 2 , 3 , (c34) 2 , 3 , c39 capacitor, ceramic, smt 0805, 0.1 f, 25 v, 10% panasonic ecj-2vb1e104k 0 0 (c5, c6) 2 , 3 capacitor, ceramic, smt 0805, 0.01 f, 50 v, 10% panasonic ecj-2yb1h103k 10 10 c11 to c14, c17 to c21, c40 capacitor, ceramic, smt 0508, 0.01 f, 50 v, 0.2% presidio components 0508x7r103m2p3 0 0 (c27, c28) 2 capacitor, ceramic, smt 0805, limits amp bandwidth as warranted 1 1 cr1 3 diode, dual schottky hsms2812, sot-23, 30 v, 20 ma panasonic ma716-(tx) 1 1 e1 install jumper wire (across opt_lat and buflat) 5 5 f1 to f5 emi suppression ferrite chip, smt 0805 steward hz0805e601r-00 1 1 j1 header, 6-pin, pin strip, 5 mm pitch wieland z5.530.0625.0 1 1 j1 pin strip, 6-pin, 5 mm pitch wieland 25.602.2653.0 1 1 j2 header, 40-pin, male, right angle samtec tsw-120-08-t-d-ra 2 2 (j3) 2 , j4, j5 connector, gold, female, coax., sma, vertical johnson components 142-0701-201 1 1 l1 inductor, smt, 1008-ct package, 4.7 nh coilcraft 1008ct-040x-j 0 0 (r1) 2 , 3 resistor, thick film, smt 0402, 100 , 1/16 w, 1% panasonic erj-2rkf1000 0 0 (r2) 2 resistor, thick film, smt 1206, 60.4 , 1/4 w, 1% panasonic erj-8enf60r4v 2 2 (r3 to r5) 1 , 2 , (r8) 1 , 2 , r9, r10 resistor, thick film, smt 0805, 500 , 1/8 w, 1% panasonic erj-6enf4990v 2 2 r6, r7 resistor, thick film, smt 0805, 25.5 , 1/8 w, 1% panasonic erj-6enf25r5v 0 0 (r11) 2 , 3 , (r13) 2 , 3 resistor, thick film, smt 0805, 66.5 , 1/8 w, 1% panasonic erj-6enf66r5v 0 0 (r12) 2 , 3 , (r14) 2 , 3 resistor, thick film, smt 0805, 100 , 1/8w, 1% panasonic erj-6enf1000v 1 1 r15 1 resistor, thick film, smt 0402, 178 , 1/16 w, 1% panasonic erj-2rkf1780x 1 1 r35 resistor, thick film, smt 0805, 49.9 , 1/8 w, 1% panasonic erj-6enf49r9v 4 4 rn1 to rn4 resistor array, smt 0402; 100 ; 8 iso res.,1/4 w; 5% panasonic exb2hv101jv 2 2 t2 3 , t3 1 transformer, adt4-1wt, cd542, 2 mhz to 775 mhz mini-circuits adt4-1wt 1 0 u1 ic, 14-bit, 80 msps adc analog devices ad6645asq/asv-80 0 1 u1 ic, 14-bit, 105 msps adc analog devices ad6645asq/asv-105 2 2 u2, u7 ic, soic-20, octal d-type flip-flop fairchild 74lcx574wm 0 0 (u3) 1 , 2 ic, soic-8, low distortion differential adc driver analog devices ad8138ar 2 2 u4, u6 ic, sot-23, tiny logic uhs 2 input or gate fairchild nc7sz32
ad6645 rev. d | page 21 of 24 quantity 80 msps quantity 105 msps reference id description manufacturer supplier part no. 0 0 (u8) 2 , 3 ic, soic-8, differential receiver motorola mc100lvel16 1 0 y1 clock oscillator, 80 mhz cts reeves mxo45-80 4 4 y1 pin sockets, closed en d amp/tyco electronics 5-330808-3 4 4 circuit board support richco, inc. cbsb-14-01 1 ac-coupled ain is standard: r3, r4, r5, r8, and u3 are not inst alled. if dc-coupled ain is required, c30, r15, and t3 are not installed. 2 reference designators in parentheses are not installed on standard units. 3 ac-coupled encode is standard: c5, c6, c33, c34, r1, r11 to r14, and u8 are not installed. if pecl encode is required, cr1 and t2 are not installed.
ad6645 rev. d | page 22 of 24 0.0 74lcx574 cp d0 d1 d2 d3 d4 d6 d7 gnd o0 o1 o2 o3 o4 o5 o6 o7 vcc oe d5 vee q q vcc d d nc vbb 0.0 vcc gn d out oe oe' gnd' vcc' out' ain c1 c2 d0 d1 d10 d11 d12 d13 d2 d3 d4 d5 d6 d7 d8 d9 dr y enc vref ain enc gnd gnd gnd dvcc avcc avcc gnd gnd avcc dvcc gnd avc c gn d avc c gn d avc c gn d gn d avc c gn d gn d avc c dvc c gn d gnd gnd avcc dnc ovr dmid gnd +v gnd +v header40 74lcx574 cp d0 d1 d2 d3 d4 d6 d7 gnd o0 o1 o2 o3 o4 o5 o6 o7 vcc oe d5 do not install install jumper optional (see note 1) 1. r2 is installed for input matching on the primary of t3. r1 5 is not installed. r15 is installed for input matching on the secondary of t3, r2 is not installed. 3. ac-coupled encode is standard. c5, c6, c33, c34, r1, r11 ? r14 and u8 are not installed. notes: 2. ac-coupled ain is standard, r3, r4, r5, r8 and u3 are not installed. enc if dc-coupled ain is required, c30, r15 and t3 are not installed. ain if pecl encode is required, cr1 and t2 are not installed. (see note 1) (see note 2) dc-coupled ain option 80mhz (ad6645) 66.66mhz (ad6644) ad6644/ad6645 4:1 impedance ratio 4:1 impedance ratio do not install dc-coupled encode option (see note 3) opt_clk do not install do not install j5 j3 j4 r2 60.4 7 02 1 12 13 14 15 16 17 18 19 10 9 8 6 5 4 3 2 11 u2 1 10 11 12 13 14 15 16 17 18 19 2 20 21 22 23 24 25 26 27 28 29 3 30 31 32 33 34 35 36 37 38 39 4 40 56 78 9 j2 l1 4.7nh 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 rn4 100 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 rn3 100 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 rn2 100 1 10 11 12 13 14 15 16 2 3 4 5 6 7 89 rn1 100 1 2 3 4 5 6 j1 f1 3 16 5 4 t2 adt4-1wt +3p3vin 10u c31 -5v +3p3v_xtl 10u c2 e1 e2 ovr e6 2 1 5 3 4 nc7sz32 u6 4 3 5 1 2 u4 nc7sz32 r10 500 r9 500 c7 0.1u c8 0.1u 2 3 4 5 6 7 8 9 10 11 12 13 40 41 42 44 454647 48 4950 52 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 232221 20 19 18 17161514 1 51 43 u1 0.1u c32 0.01u c5 r1 100 0.01u c6 enc enc 0.1u c15 0.1u c22 +5va 12 f3 +3p3v_xtl 12 f5 14 78 1 3 5 12 10 y1 +3p3vd +3p3v pref c1 10u c38 10u 0.1u c33 0.1u c34 f2 r13 66.5 r14 100 +5va r12 100 r11 66.5 0.01u c4 0 c39 0.1u 3 2 1 cr1 0.1u c30 c27 0.1u c29 c 4 0.1u c3 0.1u r8 500 r 5 500 500 r3 c26 0.1u c25 0.1u 0.1u c24 0.1u c23 0.01u c14 0.01u c13 0.01u c12 0.01u c11 0.1u c10 0.1u c9 c16 0.1u c17 0.01u c18 u10.0 u10.0 c21 c20 0.01u 0.01u c19 +5va +5v +3p3v 12 f4 +3p3vd +3p3vin ain r6 25.5 r7 25.5 +5va +5va +3p3v +3p3vd buflat buflat 3 u3 r4 5 6 7 8 3 2 1 4 u8 mc100lvel16 r15 178 +5va +3p3vd 7 02 1 12 13 14 15 16 17 18 19 10 9 8 6 5 4 3 2 11 u7 49.9 r35 opt_lat +3p3v +3p3v +5v a +5v a +5v a +5v a +5v a +5va +5va dr _ou t gn d vref -5v ain c28 +5va vref +3p3v d buflat buflat dr_out 3 16 5 4 t3 adt4-1wt b00 b01 b02 b03 b04 b05 b06 b07 b08 b09 b10 b11 b12 b13 ad8138arm +5va 4 5 500 6 2 7 val v+ v ? nc vocm 8 1 02647-043 figure 43. evaluation board schematic
ad6645 rev. d | page 23 of 24 02647-044 figure 44. top signal level 02647-045 figure 45. 5.0 v plane layer 3 and 3.3 v plane layer 4 02647-046 figure 46. ground plane layer 2 and ground plane layer 5 0 2647-047 figure 47. bottom signal layer
ad6645 rev. d | page 24 of 24 outline dimensions compliant to jedec standards ms-026-bcc-hd 0.65 bsc lead pitch 0.38 0.32 0.22 exposed heat sink (centered) bottom view (pins up) 1 . 6 0 m a x v i e w a p i n 1 0 . 7 5 0 . 6 0 0 . 4 5 40 52 40 52 14 13 26 14 26 27 39 27 39 top view (pins down) 1 13 1 0.20 0.08 1.45 1.40 1.35 0.10 max coplanarity view a rotated 90 ccw seating plane 7 0 0.15 0.05 12.20 12.00 sq 11.80 10.20 10.00 sq 9.80 2.65 2.50 (4 plcs) 2.35 2.35 2.20 (4 plcs) 2.05 6.05 5.90 sq 5.75 082108-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 48. 52-lead low profile quad flat package, powerquad [lqfp_pq4] (sq-52-1) dimensions shown in millimeters compliant to jedec standards ms-026-acc 40 52 1 14 13 26 27 39 12.00 bsc sq 10.00 bsc sq 1.20 max 0.75 0.60 0.45 view a top view (pins down) pin 1 40 52 14 1 13 26 27 39 0.65 bsc lead pitch 0.38 0.32 0.22 bottom view (pins up) 6.50 bsc sq exposed pad 072408-a for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. seating plane 1.05 1.00 0.95 0.20 0.09 0.08 max coplanarity view a rotated 90 ccw 0 min 7 3.5 0 0.15 0.05 figure 49. 52-lead thin quad flat package, exposed pad [tqfp_ep] (sv-52-1) dimensions shown in millimeters ordering guide model temperature range package description package option AD6645ASQ-80 ?40c to +85c 52-lead low profile quad flat package, powerquad (lqfp_pq4) sq-52-1 ad6645asqz-80 1 ?40c to +85c 52-lead low profile quad flat package, powerquad (lqfp_pq4) sq-52-1 ad6645asvz-80 1 ?40c to +85c 52-lead thin quad flat package, exposed pad [tqfp_ep] sv-52-1 ad6645asq-105 ?10c to +85c 52-lead low profile quad flat package, powerquad (lqfp_pq4) sq-52-1 ad6645asqz-105 1 ?10c to +85c 52-lead low profile quad flat package, powerquad (lqfp_pq4) sq-52-1 ad6645asvz-105 1 ?10c to +85c 52-lead thin quad flat package, exposed pad [tqfp_ep] sv-52-1 ad6645-80/pcbz 1 evaluation board ad6645-105/pcbz 1 evaluation board 1 z = rohs compliant part. ?2002C2008 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d02647-0-10/08(d)

▲Up To Search▲

Price & Availability of AD6645ASQ-80

	To Download AD6645ASQ-80 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .